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University of California College of Engineering Department of Electrical Engineering and Computer Science J. M. Rabaey 511 Cory Hall TuTh3:30-5pm e141@eecs
EECS 141: SPRING 98 — FINAL
For all problems, you can assume the following transistor parameters:
NMOS:
VTn = 0.75V, k’n = 20 μA/V^2 , λ= 0, γ= 0.5 V1/2, 2Φ (^) F = -0.6V, LD = 0.15 μm
PMOS:
VTp = -0.75V, k’p = 7 μA/V^2 , λ= 0, γ= 0.5 V1/2, 2Φ (^) F = -0.6V, LD = 0.15 μm
NAME
Last First
GRAD/UNDERGRAD
Total
Problem 2:
Problem 1:
Problem 3:
Problem 4:
Problem 5:
Problem 6:
Have a wonderful summer!
Problem 1: Multivibrators
a. Shown in Figure 1 is a novel design of a Schmitt trigger. Determine the (W/L) ratio of transistor M1 so that VM+ = 3 VTn. VDD = 3.3V. You may ignore the body effect in this question. State clearly your other assumptions.
b. Determine approximately the value of VM-.
Vin
VDD^ Vout
VDD
FIG. 1 Schmitt trigger. Numbers on transistors indicate (W/L) ratio’s.
1
2.
?
10
M
(W/L)M1=
VM-=
Problem 2. Logic
Consider the logic family shown in Figure 3.
a. Explain in a couple of sentences the advantage of using the clocking strategy shown in Figure 3.
b. Mark the characteristics that are valid for this logic family. o Clock-feedthrough helps to improve the performance o Cascading gates can lead to problems o The preferred logic gate from a power perspective is the NAND gate o Cooling the circuit helps to reduce the minimum clock frequency.
FIG. 3 Novel logic family
advantage 1.
advantage 2.
advantage 3.
c. Two chips operating at different voltages have to be connected together. The straightforward approach would be to just connect the output and input gates, as shown in Figure 4. Mention 3 major problems of this approach.
d. Propose TWO simple modifications in the circuit to deal with most of the men- tioned problems. YOU MAY AT MOST ADD ONE TRANSISTOR.
1.1 V 3.3 V
FIG. 4 Interconnecting chips operating at different voltages
problem 1.
problem 2.
problem 3.
b. The goal of the designers is to reach of a 500 MHz clock speed. Determine the maximum delay of the logical function blocks given that only 75% of the clock period can typically used for computation (due to set-up and hold times of the registers). Also, note that the maximum internal skew within a processor module equals 150 psec.
c. The Intel designers forgot to account for one thing though. Due to the parameters variations over the die, it is observed that the delay of the clock buffers can vary over 25% (in both positive and negative directions). Determine the worst-case clock speed due to these variations.
tplogic =
fmax =
Problem 4: Memory
Consider the memory architecture shown in the Figure below.
a. Draw the (approximated) waveforms for the signals mentioned.
FIG. 6 Memory architecture
Vdd
0
Vdd
0
Vdd
0
Vdd
0
Vdd
0
Vdd
0 Vdd
0
R
DS
DS
PC
CS
D
D
Problem 5: Interconnect
An ee141 student (unnamed) figures out (s)he can get a successful multi-million $ start-up going by designing receivers (RX) for systems as defined below. Assume that the transmission line is implemented on a PCB with ν = 13 cm/nsec. Assume also CMOS full- wing levels for the TX input.
a. Unfortunately, the designer of the TX does not understand transmission lines and sets Rs to 10 Ω. Draw the lattice diagram that includes the first three values of VL.
VDD=3V
Z 0 =100 Ohm, l=10cm
RS
RL=infinity VS VL TX RX
?/
?/
10/
20/
IN OUT
the correct way to draw a PMOS says Turi; he’s wrong of course.
FIG. 7 Transmitter-Receiver combination
b. Using your answer in part a, or a stated assumption regarding the waveform at VL , derive the transistor sizing for the receiver (shown in the figure above) that prevents glitching after an initial signal transition , but requires the smallest input swing (hint: pick the smallest transistors that still avoid glitches).
c. After raising hell with the TX designer, Rs is raised to 500 Ω, and our ee141 grad- uate replaces the receiver drawn with a conventional inverter. What is the shortest clock period that allows VL to reach 50% of its final value? (assume VM = VDD /2 and that the TX input switches instantaneously).
Tmin =
d. Derive an expression for the minimum delay in the latter case.
