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Module 1: Multi-core: The Ultimate Dose of Moore's Law
Lecture 2: Introduction to Multi-core Architecture
The Lecture Contains:
Scaling Issues
Multi-core
Thread-level Parallelism
Communication in Multi-core
Tiled CMP (Hypothetical Floor-plan)
Shared Cache CMP
Niagara Floor-plan
Implications on Software
Research Directions
References
Module 1: Multi-core: The Ultimate Dose of Moore's Law
Lecture 2: Introduction to Multi-core Architecture
Scaling Issues
Hardware for extracting ILP has reached the point of diminishing return Need a large number of in-flight instructions Supporting such a large population inside the chip requires power-hungry delay- sensitive logic and storage Verification complexity is getting out of control How to exploit so many transistors? Must be a de-centralized design which avoids long wires
Multi-core
Put a few reasonably complex processors or many simple processors on the chip Each processor has its own primary cache and pipeline Often a processor is called a core Often called a chip-multiprocessor (CMP) Did we use the transistors properly? Depends on if you can keep the cores busy Introduces the concept of thread-level parallelism (TLP)
Module 1: Multi-core: The Ultimate Dose of Moore's Law
Lecture 2: Introduction to Multi-core Architecture
Communication in Multi-core
Ideal for shared address space Fast on-chip hardwired communication through cache (no OS intervention) Two types of architectures Tiled CMP: each core has its private cache hierarchy (no cache sharing); Intel Pentium D, Dual Core Opteron , Intel Montecito, Sun UltraSPARC IV, IBM Cell (more specialized) Shared cache CMP: Outermost level of cache hierarchy is shared among cores; Intel Woodcrest (server-grade Core duo), Intel Conroe (Core2 duo for desktop), Sun Niagara, IBM Power4, IBM Power
Tiled CMP (Hypothetical Floor-plan)
Module 1: Multi-core: The Ultimate Dose of Moore's Law
Lecture 2: Introduction to Multi-core Architecture
Shared Cache CMP
Niagara Floor-plan
Module 1: Multi-core: The Ultimate Dose of Moore's Law
Lecture 2: Introduction to Multi-core Architecture
References
A good reading is Parallel Computer Architecture by Culler, Singh with Gupta Caveat: does not talk about multi-core, but introduces the general area of shared memory multiprocessors Papers Check out the most recent issue of Intel Technology Journal http://www.intel.com/technology/itj/ http://www.intel.com/technology/itj/archive.htm Conferences: ASPLOS, ISCA, HPCA, MICRO, PACT Journals: IEEE Micro, IEEE TPDS, ACM TACO
