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University of California College of Engineering Department of Electrical Engineering and Computer Science J. M. Rabaey 203 McLaughlin MWF 10-11am e141@zabriskie
EECS 141: FALL 95— MIDTERM 1
For all problems, you can assume the following transistor parameters:
NMOS:
VT n = 0.75V, k’n = 20 μA/V^2 , λ = 0, γ= 0.5 V1/2, 2Φ (^) F = -0.6V
PMOS:
VT p = -0.75V, k’p = 7 μA/V^2 , λ = 0, γ= 0.5 V1/2, 2Φ (^) F = -0.6V
For all problems, you maty assume that the transistor lengths indicated are the effective lengths ( Leff ) or, equivalently, that LD = 0.
NAME
Last First
GRAD/UNDERGRAD
Total
Problem 2:
Problem 1:
PROBLEM 1: MOS Inverter
Consider the fictitious gate of Figure 1. The I-V characteristic of the load device L 1 is given in the Figure as well.
a. Determine (W/L)M 1 such that a VOL of 1V is obtained.
b. Write down the equation(s) you would use to solve for VIH.
FIG. 1 MOS Inverter
5V
M 1
Out
I
In
+ − V L^1
V
I 1 mA
2.5 V 5 V
I = 0.4 × 10 -3^ V
(W/L)
0.5 pF
W/L =
Eq. 1:
(Eq. 2:)
Property (a) or (b) Why
VOL
tpLH
tpHL
Pstat
Problem 2: Combinational Logic
The gate below has the advantage of being simple and requiring the minimum number of transistors for the function intended.
a. Derive the boolean expression for F. What logic function does this gate implement?
b. Determine the exact output voltage for each of the following conditions (assume that the supply rails — and the logic levels at the inputs — are set at 0 V and 3.3 V):
A = 0; X = 1, Y = 1 Vout =
A = 1; X = 1, Y = 1 Vout =
B = 0; X = 0, Y = 1 Vout =
B = 1; X = 0, Y = 1 Vout =
D = 0; X = 0, Y = 0 Vout =
D = 1; X = 0, Y = 0 Vout =
FIG. 3 : Complex Gate
A B
C D
X
X
X
Y
Y
F
m
n
F =
Logic function:
