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Design with PLDs and FPGAs Laboratory(11EC312L)
DESIGN AND IMPLEMENTATION OF
TRAFFIC LIGHTS CONTROLLER
USING FPGA
A Project Based Laboratory Report
in partial fulfilment for the award of III/IV B.Tech - I Semester
Submitted by
S.Najia tasleem (Reg. No.12004338) P.Manasvi (Reg. No. 12004339) D.Teja sri (Reg. No. 12004341) R.Monica (Reg. No. 12004343)
Lab Instructor
Dr.Fazal NoorBasha
Department of ECE,
KL University, Vaddeswaram, Guntur, AP – 522502
Academic Year : 2013-
Department of Electronics and Communication Engineering
KL University, Vaddeswaram, Guntur, AP – 522502
C E R T I F I C A T E
This is to certify that the mini project entitled "DESIGN AND
IMPLEMENTATION OF TRAFFIC LIGHTS CONTROLLER USING
FPGA" is for the project based laboratory for the subject “Design with
PLDs & FPGAs” done by S.NAJIA TASLEM , P.MANASVI, D.TEJA SRI,
R.MONICA bearing registration number’s R12004338,4339,4341,
is a student of III/IV B.Tech I-Semester during the academic year
2013-2014 in partial fulfilment for the award of III/IV B.Tech I-
Semester of Department of Electronics and Communication
Engineering, K L University, Vaddeswaram, Guntur, Andhra Pradesh,
INDIA.
Signature of the HOD-ECE Signature of the Lab
Faculty
technology field. In here, we would like to offer our appreciation and thanks to several
grateful and helpful individuals. Without them, this work could not have been completed and
the experience would not be so enjoyable.
We are very grateful to our esteemed Professors Dr. Fazal Noorbasha (Section Instructor),
Dr. K Harikishore, Mr.B.Kali Vara Prasad and Ms. M Preeti, Department of ECE, KL
University, Vaddeswaram, Guntur, A.P., INDIA, for their valuable guidance and creative
suggestions that helped us to complete this Lab project.
Furthermore, we are also very thankful Dr. Fazal Noorbasha, Microelectronics Group Head,
to have an opportunity to learn from him on the aspect of using the advancing FPGA
technology to improve the performance for different memory and processor applications.
Hopefully, this experience will inspire us to come up with new and interesting research ideas
in the future.
Furthermore, we want to offer our thanks to Dr. ASCS Sastry , Professor & Head,
Department ECE, KL University, Vaddeswaram, Guntur, A.P., INDIA, for providing the
required facilities to carry out the project work successfully.
We would like to thank all those helped us directly or indirectly during this
project work.
S.Najia tasleem (Reg. No.12004338)
P.Manasvi (Reg. No. 12004339)
D.Teja sri (Reg. No. 12004341)
R.Monica (Reg. No. 12004343)
ABSTRACT
The traffic in road crossings /junctions is controlled by switching ON/OFF
Red, Green & Amber lights in a particular sequence. The Traffic Light
Controller is designed to generate a sequence of digital data called switching
sequences that can be used to control the traffic lights of a typical four
roads junction in a fixed sequence. It is also proposed to implement the day
mode and night mode operations. It plays more and more important role in
modern management and control of urban traffic to reduce the accident and
traffic jam in road. It is a sequential machine to be analyzed and
programmed through a multistep process. The device that involves an
analysis of existing sequential machines in traffic lights controllers, timing
and synchronization and introduction of operation and flashing light
synthesis sequence. The methods that are used in this project are design
the circuit, write a coding, simulation, synthesis and implement in
hardware. In this project, XILINX Software was chosen to design a
schematic using schematic edit, writes a coding using Verilog HDL
(Hardware Description Language) text editor and implements the circuit on
Programmable Logic Device [PLD].
CONTENTS
Certificate i Declaration ii Acknowledgements iii Abstract iv List of Figures V List of Tables Vi Contents Vii
Chapter – 1 Introduction 1- 1.1 Traffic lights 1 1.2 Electronic design with FPGA’S 2 1.3 FPGA design flow 3
Chapter – 2 System Block Diagram and Working Principle 3- 2.1 System block diagram 3 2.2 Working Principle 4
Chapter – 3 5- System Modeling 5
Chapter – 4 Implementation results 7-
4.1 System Analysis 7 4.2 Results Report 8
Chapter 5 Conclusions and Applications 9- 5.1 Conclusion 9 5.2 Applications 10
Appendix 11- Appendix – A: Verilog Code and Test Bench 11 Appendix – B: References (^) 13
Chapter – 1 INTRODUCTION
1.1 Need for Traffic Light Controller
Traffic congestion is a severe problem in many modern cities around the world. Traffic congestion has been causing many critical problems and challenges in the major and most populated cities. To travel to different places within the city is becoming more difficult for the travelers in traffic. Due to these congestion problems, people lose time, miss opportunities, and get frustrated. Traffic congestion directly impacts the companies. Due to traffic congestions there is a loss in productivity from workers, trade opportunities are lost, delivery gets delayed, and thereby the costs goes on increasing. To solve these congestion problems, we have to build new facilities & infrastructure but at the same time make it smart. The only disadvantage of making new roads on facilities is that it makes the surroundings more congested. So for that reason we need to change the system rather than making new infrastructure twice. Therefore many countries are working to manage their existing transportation systems to improve mobility, safety and traffic flows in order to reduce the demand of vehicle use. Therefore, many researches about traffic light system have been done in order to overcome some complicated traffic phenomenon but existent research had been limited about present traffic system in well- travelled traffic scenarios. The time of allocation is fixed from east to west or opposite way and from north to south way in crossroads. Field Programmable Gate Arrays (FPGAs) are extensively used in rapid prototyping and verification of a conceptual design and also used in electronic systems when the mask-production of a custom IC becomes prohibitively expensive due to the small quantity. Many system designs that used to be built in custom silicon VLSI are now implemented in Field Programmable Gate Arrays. This is because of the high cost of building a mask production of a custom VLSI especially for small quantity.
- Physical design is “hands-off”
FPGA is an Integrated Circuit consisting of an array of uncommitted elements; interconnection between these elements is user-programmable. Using Random Access Memory, high density logic is provided. FPGA is advantageous compared to microcontroller in terms of number of IO (input & output) ports and performance. FPGA, an inexpensive solution compared to ASIC design; is effective with respect to cost in the case of production of large number of units but for fabrication in small number of units it is always costly and time consuming. The Design flow of FPGA shown in Fig. 1 is used to implement the traffic light controller using FPGA. The circuit description can be done using HDLs, followed by the functional simulation and synthesis. The design flow is followed till the timing simulation and then the generated file is downloaded into the target device (FPGA). Verilog is used as HDL for circuit description to code the TLC module. Verilog HDL is used because of the difficulty in writing a VHDL code which has to integrate the source code, ChipScope Pro-Integrated Controller (ICON) and Virtual Input Output (VIO).
1.3 FPGA Design Flow
A simplified version of design flow is given in the flowing diagram.
Fig 1.1 FPGA Design Flow
Implementation This process consists a sequence of three steps
- Translate
- Map
- Place and Route
Translate process combines all the input netlists and constraints to a logic design file. This information is saved as a NGD (Native Generic Database) file. This can be done using NGD Build program. Here, defining constraints is nothing but, assigning the ports in the design to the physical elements (ex. pins, switches, buttons etc) of the targeted device and specifying time requirements of the design. This information is stored in a file named UCF (User Constraints File). Tools used to create or modify the UCF are PACE, Constraint Editor etc.
Fig 1.3 FPGA Translate
Map process divides the whole circuit with logical elements into sub blocks such that they can be fit into the FPGA logic blocks. That means map process fits the logic defined by the NGD file into the targeted FPGA elements (Combinational Logic Blocks (CLB), Input Output Blocks (IOB)) and generates an NCD (Native Circuit Description) file which physically represents the design mapped to the components of FPGA. MAP program is used for this purpose.
Fig 1.4 FPGA map Place and Route PAR program is used for this process. The place and route process places the sub blocks from the map process into logic blocks according to the constraints and connects the logic blocks. Ex. if a sub block is placed in a logic block which is very near to IO pin, then it may save the time but it may affect some other constraint. So trade off between all the constraints is taken account by the place and route process. The PAR tool takes the mapped NCD file as input and produces a completely routed NCD file as output. Output NCD file consists the routing information.
Fig 1.5 FPGA Place and route
Device Programming Now the design must be loaded on the FPGA. But the design must be converted to a format so that the FPGA can accept it. BITGEN program deals with the conversion. The routed NCD file is then given to the BITGEN program to generate a bit stream (a .BIT file) which can be used to configure the target FPGA device. This can be done using a cable. Selection of cable depends on the design.
Design Verification
Verification can be done at different stages of the process steps.
Chapter – 2 Design of Traffic Light Controller
Traffic Light Controller can be designed by starting with some arbitrary assumptions. At first the North traffic will be allowed to move and then traffic in the East, South and West direction will be allowed to move in sequence. The advantage of writing Traffic Light Controller program is that in a program, modifications as per requirements can be done easily i.e., suppose the traffic on main road should be allowed for more time and for side roads the traffic should be allowed for less time; then the clock is divided in such a way that for main road the clock period will be more and for side roads the clock period will be less, this is because the main road traffic is heavy when compared to the side road traffic. In general TLC System will be having three lights (red, green and yellow) in each direction where red light stands for traffic to be stopped, green light stands for traffic to be allowed and yellow light stands for traffic is going to be stopped in few seconds.
Fig 2.1 TLC Flow Chart
2.1 Explanation of Traffic Light Controller
In this structure, there are four traffic signals, represented by R1, R2, R and R4 to be controlled. All the four signals have same priority as they all are main roads.
Fig 2.2 Traffic Signals at Junction
First of all the signal controller is in the reset mode where in the signal of road (R1) is green whereas all the other roads R2, R3 and R4 are red. This state we have assigned as S0.
Later the controller sends the control to state S1 where the R1 is yellow whereas all the other signals are still red only. In this state the controller checks whether the sensor at road R2 which is X2 is low or not. If the sensor gives a low signalling that there is no traffic on that road, then that signal on road R2 is skipped transferring control to the state S4 where signal on road R3 is turned whereas rest of the signals are showing red. On the hand if the traffic is present on the road R2 then the control is sent to state S2 which switches on the signal on road R2 to green and rest of the signals are red only when the control is with state S2 after showing the green signal the signal light changes from green to yellow for signal on the
yellow light (y2) and pedestrian east will be ON and then dir is incremented by one and cnt is assigned to zero.
Fig 2.3 TLC State Diagram
So whenever cnt=00 and dir=10, the green light in south direction will be ON for few seconds and all red lights in other directions will be ON. Whenever cnt=01 and dir=10 then yellow light (y1) will be ON for few seconds and when cnt=01 yellow light (y2) and pedestrian south will be ON and then dir is incremented by one and cnt is assigned to zero. So whenever cnt=00 and dir=11, the green light in west direction will be ON for few seconds and all red lights in other directions will be ON. Whenever cnt= and dir=11 then yellow light (y1) will be ON for few seconds and when cnt=01 yellow light (y2) and pedestrian west will be ON and then dir is assigned to 00 and cnt is assigned to zero. This sequence repeats and the traffic flow will be controlled by assigning time periods in all the four directions.
Chapter – 3
Simulation Results
3.1 RTL Schematic
The below figure shows the RTL Schematic of the Traffic Light Controller.
Fig 3.1 RTL Schematic
