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An overview of combinational logic in verilog, focusing on the creation of combinational components, specifically multiplexers. It covers the basics of combinational logic, the recipe for creating combinational components, and an example implementation of a multiplexer in systemverilog.
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Typology: Cheat Sheet
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SystemVerilog
module MY_SYSTEM(A, B, C); input A, B; output C;
assign C = A ^ B; endmodule
module MY_SYSTEM_2(A, B, C); input A, B; output C;
wire S0, S1;
assign S0 = A & ~B; assign S1 = ~A & B; assign C = S1 | S0; endmodule
Recipe to Create Combinational Components
always @(/* sensitivity list /) begin / combinational stements */ end
SystemVerilog
SystemVerilog
SystemVerilog
2'b01: Y = X[ 1 ]; 2'b10: Y = X[ 2 ]; 2'b11: Y = X[ 3 ]; endcase endmodule
module mux(input [ 3 : 0 ] X, input [ 1 : 0 ] SW, output Y); always_comb case (SW) 2'b01: Y = X[ 1 ]; 2'b10: Y = X[ 2 ]; 2'b11: Y = X[ 3 ]; default: Y = X[ 0 ]; endcase endmodule
SystemVerilog