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Network Exam: Multicast Virtual Circuits and Load Balancing, Exams of Design and Analysis of Algorithms

A part of an exam focusing on multicast virtual circuits in networking. It covers topics such as load calculation, network design, and speed requirements for non-blocking networks. The document also discusses the use of wugs switches and their range-copy mechanism for implementing multicast virtual circuits.

Typology: Exams

2012/2013

Uploaded on 03/23/2013

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Exam 2, Part B
November 21, 1997
In this part of the exam, you may use one page of notes and a calculator.
1. (50 points) Let
N
[2]
=
N
N
,
N
[3]
=
N
(
N
N
)) and so forth. So for example,
D
n;d
=
X
[
k
]
d;d
if
k
= log
d
n
.Now, let
H
(
n; d
1
;d
2
;h;r
)=
8
>
<
>
:
X
[
h
]
d
1
;d
1
X
[
k
,
h
]
d
1
;d
1
(
X
[
h
,
r
]
d
1
;d
1
X
[
r
]
d
1
;d
2
) if
r
h
X
[
h
]
d
1
;d
1
(
X
[
k
,
r
]
d
1
;d
1
X
[
r
,
h
]
d
1
;d
2
)
X
[
h
]
d
1
;d
2
if
r
h
Note that if
d
1
=
d
2
that
H
(
n; d
1
;d
2
;h;r
)
D
n;d
1
;h
. Draw pictures of
H
16
;
2
;
3
;
2
;
1
and
H
16
;
2
;
3
;
2
;
3
.
1
pf3
pf4
pf5
pf8

Partial preview of the text

Download Network Exam: Multicast Virtual Circuits and Load Balancing and more Exams Design and Analysis of Algorithms in PDF only on Docsity!

Exam 2, Part B

Novemb er 21, 1997

In this part of the exam, you may use one page of notes and a calculator.

  1. (50 p oints) Let N [2]^ = N  N , N [3]^ = N  (N  N )) and so forth. So for example, Dn;d = X (^) d;d[k^ ] if k = log (^) d n. Now, let

H (n; d 1 ; d 2 ; h; r ) =

X (^) d[h 1 ] ;d 1 X (^) d[k 1 ;dh 1 ] (X (^) d[h 1 ;dr 1 ]  X (^) d[r 1 ] ;d 2 ) if r  h

X (^) d[h 1 ] ;d 1 (X (^) d[k 1 ;dr 1 ]  X (^) d[r 1 ;dh 2 ] ) X (^) d[h 1 ];d 2 if r  h

Note that if d 1 = d 2 that H (n; d 1 ; d 2 ; h; r )  D  n;d 1 ;h. Draw pictures of H 16 ; 2 ; 3 ; 2 ; 1 and H 16 ; 2 ; 3 ; 2 ; 3.

Supp ose this network is used to implement a multicast ATM switch with dynamic routing (the rst h stages distribute trac, the remaining k stages route and copy cells to the outputs). Let (cj ) b e the load that a virtual circuit (xj ; Yj ; !j ) places on a link where xj is an input, Yj is a set of outputs and !j is a weight b etween zero and 1, representing the bandwidth of the virtual circuit's data stream, relative to the rate of the internal links. If is in stage i and is on some path from x to one or more outputs in Y , what is the load that cj induces on if i  h?

What if i  k?

What if h < i < k?

How many inputs can reach link ` if i  h?

What if h < i < k?

If the total trac on each input and each output is  , what is the maximum load that can b e placed on link ` if i  h?

What if i  k?

What if h < i < k?

What sp eed advantage is required to make this network nonblo cking?

with fanout 2 f and bandwidth B? (You may assume that f divides evenly into n.)

What do es this imply ab out the sp eed advantage that the system requires in order to b e nonblo cking?

If ( =B ) = 16, what is the actual value of the required sp eed advantage for virtual circuits with fanout 4, 16 and 64? How do es this compare with the case where we use binary copying and allow the numb er of recyling passes to increase with the fanout?

How would the results ab ove change, if the load on di erent recycling paths were guaranteed to di er by at most some value ?